Dear Trnsys users I really cannot find out what is wrong with the attached project. Simulation fails if started at any time but 0 due to inconsistency between current time step and current interpolation interval in Type16. However when I trace Type9, the interval boundaries (outputs 99 and 100) do actually bound the current time step at any time ! Help on this reluctant issue would be much appreciated. Thanks a lot -- Antoine Gautier |
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Project22.zip
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