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Mariana, I am having a little trouble understanding whether you are trying to force Type56 to iterate within a time step or whether you are trying to prevent Type56 from iterating within a time step. Either way, it is a very complicated thing to do; Type56 not only has its own internal iterative solver but its inputs and outputs feed into the iterative solver within the TRNSYS kernel. I suspect that not only would you have to change the Type56 code but you would also have to change the kernel code as well. If you are running into convergence problems with a model, it is best to try and solve those by adjusting time steps and by looking carefully at your system and controls. There are some cases in which you might need to insert a time delay into a model. There are two models that allow you do hold on to an output for one or more time steps before releasing it. This will have the effect of preventing some iteration because an output change in one model will not be noticed by the next model until the following time step. Be very careful in implementing these components because while they are convenient and an easy way to "improve" convergence, most often it is best to solve non-convergence problems by looking carefully at time steps and controls and not by adding arbitrary delays. Best, David On 8/4/2010 04:07, ghetu mariana wrote:
-- *************************** David BRADLEY Principal Thermal Energy Systems Specialists, LLC 22 North Carroll Street - suite 370 Madison, WI 53703 USA P:+1.608.274.2577 F:+1.608.278.1475 bradley@tess-inc.com http://www.tess-inc.com http://www.trnsys.com |